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| rev. 1.3 march 2003 1/102 st7scr 8-bit low-power, full-speed usb mcu with 16k flash, 768 ram, smartcard i/f, timer n memories C up to 16k of rom or high density flash (hd- flash) program memory with read/write pro- tection, hdflash in-circuit and in-application programming. 100 write/erase cycles guaran- teed, data retention: 20 years at 55c C up to 768 bytes of ram including up to 128 bytes stack and 256 bytes usb buffer n clock, reset and supply management C low voltage reset C 2 power saving modes: halt and wait modes C pll for generating 48 mhz usb clock using a 4 mhz crystal n interrupt management C nested interrupt controller n usb (universal serial bus) interface C 256-byte buffer for full speed bulk, control and interrupt transfer types compliant with usb specification (version 2.0) C on-chip 3.3v usb voltage regulator and transceivers with software power-down C 7 usb endpoints: one 8-byte bidirectional control endpoint one 64-byte in endpoint, one 64-byte out endpoint four 8-byte in endpoints n 35 or 4 i/o ports : C up to 4 led outputs with software program- mable constant current (3 or 7 ma). C 2 general purpose i/os programmable as in- terrupts C up to 8 line inputs programmable as interrupts C up to 20 outputs C 1 line assigned by default as static input after reset n iso7816-3 uart interface: C 4 mhz clock generation C synchronous/asynchronous protocols (t=0, t=1) C automatic retry on parity error C programmable baud rate from 372 clock puls- es up to 11.625 clock pulses (d=32/f=372) C card insertion/removal detection n smartcard power supply: C selectable card v cc 1.8v, 3v, and 5v C internal step-up converter for 5v supplied smartcards (with a current of up to 55ma) us- ing only two external components. C programmable smartcard internal voltage regulator (1.8v to 3.0v) with current overload protection and 4 kv esd protection (human body model) for all smartcard interface i/os n one 8-bit timer C time base unit (tbu) for generating periodic interrupts. n development tools C full hardware/software development package table 1. device summary tqfp64 14x14 so24 features st7fscr1r4 st7scr1r4 st7fscr1e4 st7scr1e4 program memory 16k flash 16k rom 16k flash 16k rom user ram (stack) - bytes 768 (128) peripherals usb full-speed (7 ep), tbu, watchdog timer, iso7816-3 interface operating supply 4.0 to 5.5v package tqfp64 so24 cpu frequency 4 or 8 mhz operating temperature 0c to +70c 1
table of contents 102 2/102 st7scr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 program memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 6.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.2 time base unit (tbu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.3 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.4 smartcard interface (crd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1 table of contents 3/102 13 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.3 supply and reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.6 smartcard supply supervisor electrical characteristics . . . . . . . . 82 14.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.8 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 89 15 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . 92 16.1 device ordering information and transfer of customer code . . . . . 93 16.2 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.3 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 18 silicon identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 19 reference specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20.1 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20.2 usb: two consecutive setup tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20.3 usb buffer shared memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.4 wdg (watchdog) limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.5 supply current in halt mode (suspend) limitations . . . . . . . . . . . . . . . . 100 20.6 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.7 i/o port input high level (vih) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 21 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 22 errata sheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 1 to obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet please note that an errata sheet can be found at the end of this document on page 99 . st7scr 4/102 1 introduction the st7scr and st7fscr devices are mem- bers of the st7 microcontroller family designed for usb applications. all devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. the st7scr rom devices are factory-pro- grammed and are not reprogrammable. the st7fscr versions feature dual-voltage flash memory with flash programming capability. they operate at a 4mhz external oscillator fre- quency. under software control, all devices can be placed in wait or halt mode, reducing power consump- tion when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. the devices include an st7 core, up to 16 kbytes of program memory, up to 512 bytes of user ram, up to 35 i/o lines and the following on-chip periph- erals: C usb full speed interface with 7 endpoints, pro- grammable in/out configuration and embedded 3.3v voltage regulator and transceivers (no ex- ternal components are needed). C iso7816-3 uart interface with programmable baud rate from 372 clock pulses up to 11.625 clock pulses C smartcard supply block able to provide pro- grammable supply voltage and i/o voltage levels to the smartcards C low voltage reset ensuring proper power-on or power-off of the device (selectable by option) C watchdog timer C 8-bit timer (tbu) figure 1. st7scr block diagram 8-bit core alu address and data bus oscin oscout pa6 4mhz control ram (512 bytes) program (16k bytes) memory 8-bit timer lvd v pp usbdp usbdm usbvcc port c pc[7:0] pb[7:0] pa[5:0] supply manager pll oscillator usb port b port a usb data buffer (256 bytes) divider 8 mhz 3v/1.8v vreg dc/dc crddet crdio crdc4 crdc8 crdrst crdclk pd[7:0] iso7816 uart port d converter crdvcc self watchdog led led[3:0] or 4 mhz 48 mhz diode 1 st7scr 5/102 2 pin description figure 2. 64-pin tqfp package pinout wakup2/pa2 wakup2/pa3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 oscin oscout crddet vdd wakup2/iccdata/pa0 wakup2/iccclk/pa1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c4 crdio c8 gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 nc crdclk nc pa6 v pp pc7/wakup1 pc6/wakup1 pc5/wakup1 pc4/wakup1 pc3/wakup1 pc2/wakup1 pc1/wakup1 pc0/wakup1 gnd vdd nc dp dm led0 self1 self2 pa5 pa4 nc nc led3 led2 led1 vdd vdda usbvcc crdvcc gnd gnda diode crdrst nc = not connected 1 st7scr 6/102 pin description (contd) figure 3. 24-pin so package pinout 14 13 11 12 15 16 17 18 led0 dm dp usbvcc oscin oscout v pp 1 2 3 4 5 6 7 8 9 10 diode crdclk crdrst crdvcc pa6 crdio 19 20 c8 crddet iccdata/wakup2/pa0 v dda c4 gnda iccclk/wakup2/pa1 nc gnd 21 22 23 24 v dd self 1 st7scr 7/102 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 10ma high sink (on n-buffer only) port and control configuration: C input:float = floating, wpu = weak pull-up, int = in- terrupt, ana = analog C output: od = open drain, pp = push-pull refer to i/o ports on page 30 for more details on the software configuration of the i/o ports. table 1. pin description pin n pin name type level v card supplied port / control main function (after reset) alternate function tqfp64 so24 input output input output wpu int od pp 1 5 crdrst o c t x x smartcard reset 2 nc not connected 3 6 crdclk o c t x x smartcard clock 4 nc not connected 57c4 o c t x x smartcard c4 6 8 crdio i/o c t x x x smartcard i/o 79c8 o c t x x smartcard c8 8 3 gnd s ground 9 pb0 o c t x x port b0 1) 10 pb1 o c t x x port b1 1) 11 pb2 o c t x x port b2 1) 12 pb3 o c t x x port b3 1) 13 pb4 o c t x x port b4 1) 14 pb5 o c t x x port b5 1) 15 pb6 o c t x x port b6 1) 16 pb7 o c t x x port b7 1) 17 10 crddet i c t x smartcard detection 18 vdd s power supply voltage 4v-5.5v 19 11 pa0/wakup2/ iccdata i/o c t x x x x port a0 interrupt, in-circuit communication data input 20 12 pa1/wakup2/ iccclk i/o c t x x x x port a1 interrupt, in-circuit communication clock input 21 pa2/wakup2 i/o c t x x x x port a2 1) interrupt 22 pa3/wakup2 i/o c t x x x x port a3 1) interrupt 23 pd0 o c t x x port d0 1) 24 pd1 o c t x x port d1 1) 25 pd2 o c t x x port d2 1) 1 st7scr 8/102 26 pd3 o c t x x port d3 1) 27 pd4 o c t x x port d4 1) 28 pd5 o c t x x port d5 1) 29 pd6 o c t x x port d6 1) 30 pd7 o c t x x port d7 1) 31 14 oscin c t input/output oscillator pins. these pins connect a 4mhz parallel-resonant crystal, or an external source to the on-chip oscillator. 32 15 oscout c t 33 vdd s power supply voltage 4v-5.5v 34 gnd s ground 35 pc0/wakup1 i c t x x pc0 1) external interrupt 36 pc1/wakup1 i c t x x pc1 1) external interrupt 37 pc2/wakup1 i c t x x pc2 1) external interrupt 38 pc3/wakup1 i c t x x pc3 1) external interrupt 39 pc4/wakup1 i c t x x pc4 1) external interrupt 40 pc5/wakup1 i c t x x pc5 1) external interrupt 41 pc6/wakup1 i c t x x pc6 1) external interrupt 42 pc7/wakup1 i c t x x pc7 1) external interrupt 43 16 v pp s flash programming voltage. must be held low in nor- mal operating mode. 44 17 pa6 i c t pa6 45 18 led0 o hs x constant current output 46 19 dm i/o c t usb data minus line 47 20 dp i/o c t usb data plus line 48 nc not connected 49 21 usbvcc o c t 3.3 v output for usb 50 22 v dda s power supply voltage 4v-5.5v 51 23 v dd s power supply voltage 4v-5.5v 52 led1 o hs x constant current output 53 led2 o hs x constant current output 54 led3 o hs x constant current output 55 nc not connected 56 nc not connected 57 pa4 i/o c t x x x x port a4 pin n pin name type level v card supplied port / control main function (after reset) alternate function tqfp64 so24 input output input output wpu int od pp 1 st7scr 9/102 note 1 : keyboard interface 58 pa5 i/o c t x x x x port a5 59 24 self2 o c t an external inductance must be connected to these pins for the step up converter (refer to figure 4 to choose the right capacitance) 60 24 self1 o c t 61 1 diode s c t an external diode must be connected to this pin for the step up converter (refer to figure 4 to choose the right component) 62 2 gnda s ground 63 3 gnd s 64 4 cdrvcc o c t x smartcard supply pin pin n pin name type level v card supplied port / control main function (after reset) alternate function tqfp64 so24 input output input output wpu int od pp st7scr 10/102 pin description (contd) figure 4. smartcard interface reference application note 1: refer to section 6 on page 20 . led0 dm dp usbvcc oscin oscout v pp diode crdclk crdrst crdvcc pa6 crdio c8 crddet pa0 v dda c4 gnda pa1 nc gnd v dd self v dd c l1 c l2 c7 c8 c9 v dd l1 c5 d1 r led c4 vbus d- d+ gnd shield c2 c1 c3 c6 v dd v dd d+ d- mandatory values for the external components : c2 : 4.7 f,esr 0.5 ohm l1 : 10 h, 2 ohm c7 : 4.7 f,esr 0.5 ohm c5 : 1 nf crystal 4.0 mhz, impedance max100 ohm cl1, cl2 1) d1: bat42 shottky c6 : 100 nf c8 : 470 pf c9 : 100 pf c1 : 100nf c3 : 1 f c4 : 4.7 f r : 1.5kohm 1 st7scr 11/102 3 register & memory map as shown in figure 5 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 40 bytes of register locations, up to 512 bytes of ram and up to 16k bytes of user program memory. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. important : memory locations noted re- served must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 5. memory map 0000h interrupt & reset vectors hw registers 0040h 003fh (see table 2 ) ffdfh ffe0h ffffh (see table 7 ) c000h 033fh program memory ram usb ram (16k bytes) short addressing stack (128 bytes) 0100h 0180h 023fh 0040h 00ffh 017fh 16-bit addressing ram ram (192 bytes) ( 192 bytes) 023fh 0240h 256 bytes (512 bytes) unused 1 st7scr 12/102 table 2. hardware register memory map address block register label register name reset status remarks 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000ah 000bh 000ch 000dh crd crdcr crdsr crdccr crdetu1 crdetu0 crdgt1 crdgt0 crdwt2 crdwt1 crdwt0 crdier crdipr crdtxb crdrxb smartcard interface control register smartcard interface status register smartcard contact control register smartcard elementary time unit 1 smartcard elementary time unit 0 smartcard guard time 1 smartcard guard time 0 smartcard character waiting time 2 smartcard character waiting time 1 smartcard character waiting time 0 smartcard interrupt enable register smartcard interrupt pending register smartcard transmit buffer register smartcard receive buffer register 00h 80h xxh 01h 74h 00h 0ch 00h 25h 80h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r 000eh watchdog wdgcr watchdog control register 00h r/w 0011h 0012h 0013h 0014h port a padr paddr paor papucr port a data register port a data direction register option register pull up control register 00h 00h 00h 00h r/w r/w r/w r/w 0015h 0016h 0017h port b pbdr pbor pbpucr port b data register option register pull up control register 00h 00h 00h r/w r/w r/w 0018h port c pcdr port c data register 00h r/w 0019h 001ah 001bh port d pddr pdor pdpucr port d data register option register pull up control register 00h 00h 00h r/w r/w r/w 001ch 001dh 001eh 001fh misc miscr1 miscr2 miscr3 miscr4 miscellaneous register 1 miscellaneous register 2 miscellaneous register 3 miscellaneous register 4 00h 00h 00h 00h r/w r/w r/w r/w 1 st7scr 13/102 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h usb usbistr usbimr usbctlr daddr usbsr epor cnt0rxr cnt0txr ep1txr cnt1txr ep2rxr cnt2rxr ep2txr cnt2txr ep3txr cnt3txr ep4txr cnt4txr ep5txr cnt5txr errsr usb interrupt status register usb interrupt mask register usb control register device address register usb status register endpoint 0 register ep 0 receptioncounter register ep 0 transmission counter register ep 1 transmission register ep 1 transmission counter register ep 2 reception register ep 2 reception counter register ep 2 transmission register ep 2 transmission counter register ep 3 transmission register ep 3 transmission counter register ep 4 transmission register ep 4 transmission counter register ep 5 transmission register ep 5 transmission counter register error status register 00h 00h 06h 00h 00h 0xh 00h 00h 00h 00h 00h 0xh 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0035h 0036h tbu tbucv tbucsr timer counter value timer control status 00h 00h r/w r/w 0037h 0038h 0039h 003ah itc itspr0 itspr1 itspr2 itspr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 003bh flash fcsr flash control status register 00h r/w 003eh led_ctrl led control register 00h r/w address block register label register name reset status remarks 1 st7scr 14/102 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hd- flash) is a non-volatile memory that can be electri- cally erased as a single block or by individual sec- tors and programmed on a byte-by-byte basis us- ing an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features n three flash programming modes: C insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. C icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. C iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. n ict (in-circuit testing) for downloading and executing user application test patterns in ram n read-out protection against piracy n register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 3 ). each of these sectors can be erased independently to avoid unneces- sary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 6 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 3. sectors available in flash devices figure 6. memory map and sector address flash memory size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes sector 1 sector 0 sector 2 16k user flash memory size ffffh f000h efffh e000h dfffh c000h 8kbytes ex.: user program ex.: user data ex.: user system library + iap bootloader + library 1 st7scr 15/102 flash program memory (contd) 4.4 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 7 ). for more details on the pin locations, refer to the device pinout de- scription. icp needs six signals to be connected to the pro- gramming tool. these signals are: Cv ss : device power supply ground Cv dd : for reset by lvd C oscin: to force the clock during power-up C iccclk: icc output serial clock pin C iccdata: icc input serial data pin Cv pp : icc mode selection and programming voltage. if iccclk or iccdata are used for other purpos- es in the application, a serial resistor has to be im- plemented to avoid a conflict in case one of the other devices forces the signal level. note: to develop a custom programming tool, re- fer to the st7 flash programming and icc ref- erence manual which gives full details on the icc protocol hardware and software. 4.5 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the usb interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming oper- ation. figure 7. typical icp interface icp programming tool connector 10k w c l2 c l1 iccdata iccclk v ss v pp oscin oscout st7 he10 connector type t ot he a pp l ica tion v dd 4.7k w application board 1 2 4 6 8 10 97 5 3 programming tool icc connector icc cable 1 st7scr 16/102 flash program memory (contd) note: if the iccclk or iccdata pins are only used as outputs in the application, no signal isola- tion is necessary. as soon as the programming tool is plugged to the board, even if an icc ses- sion is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. refer to the programming tool documentation for recom- mended resistor values. 4.6 program memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memory are protected against read-out piracy (including a re-write protection). when this protection is re- moved by reprogramming the option byte, the en- tire flash program memory is first automatically erased. refer to the option byte description for more de- tails. 4.6.1 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. for details on customizing flash programming methods and in-circuit test- ing, refer to the st7 flash programming and icc reference manual. 70 00000000 1 st7scr 17/102 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 8 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 8. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1 st7scr 18/102 central processing unit (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. its a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 1 st7scr 19/102 central processing unit (contd) stack pointer (sp) read/write reset value: 017fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 9 ). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 9 C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 9. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h 1 st7scr 20/102 6 supply, reset and clock management 6.1 clock system 6.1.1 general description the mcu accepts either a 4mhz crystal or an ex- ternal clock signal to drive the internal oscillator. the internal clock (f cpu ) is derived from the inter- nal oscillator frequency (f osc ), which is 4mhz. after reset, the internal clock (f cpu ) is provided by the internal oscillator (4mhz frequency). to activate the 48-mhz clock for the usb inter- face, the user must turn on the pll by setting the pll_on bit in the miscr4 register. when the pll is locked, the lock bit is set by hardware. the user can then select an internal frequency (f cpu ) of either 4 mhz or 8mhz by programming the clk_sel bit in the miscr4 register (refer to miscellaneous registers section on page 37 ). the pll provides a signal with a duty cycle of 50 %. the internal clock signal (f cpu ) is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. figure 10. clock, reset and supply block diagram the internal oscillator is designed to operate with an at-cut parallel resonant quartz in the frequen- cy range specified for f osc . the circuit shown in figure 12 is recommended when using a crystal, and table 4 lists the recommended capacitance. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. the lock bit in the miscr4 register can also be used to generate the f cpu di- rectly from f osc if the pll and the usb interface are not active. table 4. recommended values for 4 mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). pll_ miscr4 on - - - -- - lock 4 mhz internal 8 mhz clock (f cpu ) 4 mhz pll x 12 48 mhz usb 48 mhz div (f osc ) clk_ sel r smax 20 w 25 w 70 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf 1 st7scr 21/102 clock system (contd) 6.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 11 . figure 11. .external clock source connections figure 12. crystal resonator oscin oscout external clock nc oscin oscout c oscin c oscout 1 st7scr 22/102 6.2 reset sequence manager (rsm) 6.2.1 introduction the reset sequence manager has two reset sourc- es: n internal lvd reset (low voltage detection) which includes both a power-on and a voltage drop reset n internal watchdog reset generated by an internal watchdog counter underflow as shown in figure 14 . 6.2.2 functional description the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 13 : n a first delay of 30s + 127 t cpu cycles during which the internal reset is maintained. n a second delay of 512 t cpu cycles after the internal reset is generated. it allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. n reset vector fetch (duration: 2 clock cycles) low voltage detector the low voltage detector generates a reset when v dd st7scr 24/102 interrupts (contd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: C the highest software priority interrupt is serviced, C if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 16 describes this decision process. figure 16. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and tli are non maskable and they can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, tli, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 15 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n tli (top level hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. caution : a trap instruction must not be used in a tli service routine. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 15 as a tli. caution: trap can be interrupted by a tli. n reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically nanded. n peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the interrupt mapping table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced 1 st7scr 25/102 interrupts (contd) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column exit from halt in interrupt mapping table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision proc- ess shown in figure 16 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 17 and figure 18 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 18 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 17. concurrent interrupt management figure 18. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes 1 st7scr 26/102 interrupts (contd) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see interrupt dedicated instruction set table). *note : tli, trap and reset events are non maskable sources and can interrupt a level 3 pro- gram. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. C each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. C each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. C level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and tli vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits 1 st7scr 27/102 interrupts (contd) table 6. dedicated interrupt instruction set note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. in order not to lose the current software priority level, the rim, sim, halt, wfi and pop cc instructions should never be used in an interrupt routine. table 7. interrupt mapping note 1: this interrupt can be used to exit from usb suspend mode. instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 icp flash start programming nmi interrupt fffah-fffbh 1 uart iso7816-3 uart interrupt uic fff8h-fff9h 2 usb usb communication interrupt usbistr fff6h-fff7h 3 wakup1 external interrupt port c yes fff4h-fff5h 4 wakup2 external interrupt port a yes fff2h-fff3h 5 tim tbu timer interrupt tbusr no fff0h-fff1h 6 carddet 1) smartcard insertion/removal interrupt 1) uscur yes ffeeh-ffefh 7 esusp end suspend interrupt usbistr ffech-ffedh 8 not used no ffeah-ffebh 1 st7scr 28/102 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the st7. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency. from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. 8.2 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0, to enable all interrupts. all other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 19 . figure 19. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 512 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the interrupt routine and cleared when the cc register is popped. 1 st7scr 29/102 power saving modes (contd) 8.3 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by ex- ecuting the halt instruction. the internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals. note: the pll must be disabled before a halt instruction. when entering halt mode, the i bit in the condi- tion code register is cleared. thus, any of the ex- ternal interrupts (iti or usb end suspend mode), are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a reset. the oscillator is then turned on and a stabi- lization time is provided before releasing cpu op- eration. the stabilization time is 512 cpu clock cy- cles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 20. halt mode flow chart n n external interrupt* reset halt instruction 512 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the interrupt routine and cleared when the cc register is popped. 1 st7scr 30/102 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C alternate signal input/output for the on-chip pe- ripherals. C external interrupt detection an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put. 9.2 functional description each port is associated to 4 main registers: C data register (dr) C data direction register (ddr) C option register (or) C pull up register (pu) each i/o pin may be programmed using the corre- sponding register bits in ddr register: bit x corre- sponding to pin x of the port. the same corre- spondence is used for the dr register. table 8. i/o pin functions input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. note 1 : all the inputs are triggered by a schmitt trigger. note 2 : when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. interrupt function when an i/o is configured in input with interrupt, an event on this i/o can generate an external in- terrupt request to the cpu. the interrupt sensitivi- ty is given independently according to the descrip- tion mentioned in the itrfre interrupt register. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, it masks the other ones. output mode the pin is configured in output mode by setting the corresponding ddr register bit (see table 7). in this mode, writing 0 or 1 to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pins state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. ddr mode 0 input 1 output 1 st7scr 31/102 i/o ports (contd) 9.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr register and spe- cific feature of the i/o port such as true open drain. 9.3.1 port a table 9. port a description figure 21. pa0, pa1, pa2, pa3, pa4, pa5 configuration figure 22. pa6 configuration port a i / o input output pa[5:0] without pull-up * push-pull or open drain with software selectable pull-up pa6 without pull-up - *reset state dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up 1) output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus note 1: selectable by papucr register dr sel pa d v dd diodes data bus cmos schmitt trigger 1 st7scr 32/102 i/o ports (contd) 9.3.2 ports b and d table 10. port b and d description figure 23. port b and d configuration ports b and d output * pb[7:0] push-pull or open drain with software selectable pull-up pd[7:0] *reset state = open drain dr latch dr sel v dd pa d alternate enable alternate enable alternate enable alternate pull-up 1) output p-buffer n-buffer 1 v ss v dd diodes data bus om latch pull_up latch 0 1 0 0 note 1: selectable by papucr register 1 st7scr 33/102 i/o ports (contd) 9.3.3 port c table 11. port c description figure 24. port c configuration port c input pc[7:0] with pull-up dr sel pa d alternate input v dd diodes cmos schmitt trigger data bus pull-up v dd 1 st7scr 34/102 i/o ports (contd) 9.4 register description data registers (pxdr) port a data register (padr): 0011h port b data register (pbdr): 0015h port c data register (pcdr): 0018h port d data register (pcdr): 0019h read/write reset value port a: 0000 0000 (00h) reset value port b: 0000 0000 (00h) reset value port c: 0000 0000 (00h) reset value port d: 0000 0000 (00h) bits 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken in account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital val- ue applied to the i/o pin (pin configured as input). data direction register (paddr) port a data direction register (paddr): 0012h read/write reset value port a: 0000 0000 (00h) bits 7:0 = dd7-dd0 data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (pxor) port x option register pxor with x = a, b, or d port a option register (paor): 0013h port b option register (pbor): 0016h port d option register (pdor): 001ah read/write reset value: 0000 0000 (00h) bits 7:0 = om[7:0] option register 8 bits. the or register allows to distinguish in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. 0: output open drain 1: output push-pull pull up control register (pxpucr) port x pull up register pxpucr with x = a, b, or d port a pull up register (papucr): 0014h port b pull up register (pbpucr): 0017h port d pull up register (pdpucr): 001bh read/write reset value: 0000 0000 (00h) bits 7:0 = pu[7:0] pull up register 8 bits. the pu register is used to control the pull up. each bit is set and cleared by software. 0: pull up inactive 1: pull up active 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 om7 om6 om5 om4 om3 om2 om1 om0 70 pu7 pu6 pu5 pu4 pu3 pu2 pu1 pu0 1 st7scr 35/102 i/o ports (contd) table 12. i/o ports register map address (hex.) register label 765 4 3210 11 padr reset value msb 00 00 000 lsb 0 12 paddr reset value msb 00 00 000 lsb 0 13 paor reset value msb 00 00 000 lsb 0 14 papucr reset value msb 00 00 000 lsb 0 15 pbdr reset value msb 00 00 000 lsb 0 16 pbor reset value msb 00 00 000 lsb 0 17 pbpucr reset value msb 00 00 000 lsb 0 18 pcdr reset value msb 00 00 000 lsb 0 19 pddr reset value msb 00 00 000 lsb 0 1a pdor reset value msb 00 00 000 lsb 0 1b pdpucr reset value msb 00 00 000 lsb 0 1 st7scr 36/102 10 miscellaneous registers miscellaneous register 1 (miscr1) reset value : 0000 0000 (00h) read/write writing the itifrec register enables or disables external interrupt on port c. each bit can be masked independantly. the itmx bit masks the external interrupt on pc.x. bits[7:0] = itm [7:0] interrupt mask 0: external interrupt disabled 1: external interrupt enabled miscellaneous register 2 (miscr2) reset value : 0000 0000 (00h) read/write writing the itifrea register enables or disables external interrupt on port a. bit 7 = reserved. bit 6 = crdirm crd insertion/removal interrupt mask 0: crdir interrupt disabled 1: crdir interrupt enabled bits [5:0] = itm [14:9] interrupt mask bit x of miscr2 masks the external interrupt on port a.x. bit x = itm n interrupt mask n 0: external interrupt disabled on pa.x. 1: external interrupt enabled on pa.x. 70 itm 7 itm 6 itm 5 itm 4 itm 3 itm 2 itm 1 itm 0 70 - crd irm itm 14 itm 13 itm 12 itm 11 itm 10 itm 9 1 st7scr 37/102 miscellaneous register 3 (miscr3) reset value: 0000 0000 (00h) read/write this register is used to configure the edge and the level sensitivity of the port a and port c external interrupt. this means that all bits of a port must have the same sensitivity. if a write access modifies bits 7:4, it clears the pending interrupts. ctrl0_c, ctrl1_c : sensitivity on port c ctrl0_a, ctrl1_a : sensitivity on port a miscellaneous register 4 (miscr4) reser value : 0000 0000 (00h). read/write bit 7 = reserved. bit 6 = pll_on pll activation 0: pll disabled 1: pll enabled note: the pll must be disabled before a halt instruction. bit 5 = clk_sel clock selection this bit is set and cleared by software. 0: cpu frequency = 4mhz 1: cpu frequency = 8mhz bits 4:1 = reserved. bit 0 = lock pll status bit 0: pll not locked. f cpu = f osc external clock fre- quency. 1: pll locked. f cpu = 4 or 8 mhz depending on clksel bit. 70 ctr l1_a ctr l0_a ctr l1_c ctr l0_c ---- ctr l1_x ctr l0_x external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 70 - pll _on clk_ sel - - - - lock 1 st7scr 38/102 miscellaneous registers (contd) table 13. register map and reset values address (hex.) register label 76543210 001c miscr1 reset value itm7 0 itm6 0 itm5 0 itm4 0 itm3 0 itm2 0 itm1 0 itm0 0 001d miscr2 reset value 00 itm14 0 itm13 0 itm12 0 itm11 0 itm10 0 itm9 0 001e miscr3 reset value ctrl1_a 0 ctrl0_a 0 ctrl1_c 0 ctrl0_c 0 0000 001fh miscr4 reset value 0 pll_on 0 rst_in 0 clk_se 0l 000 lock 0 1 st7scr 39/102 11 leds each of the four available leds can be selected using the led_ctrl register. two types of leds are supported: 3ma and 7ma. led_ctrl register reset value: 0000 0000 (00h) read/write bits 7:4 = ldx led enable 0: led disabled 1: led enabled bits 3:0 = ldx_i current selection on ldx 0: 3ma current on ldx pad 1: 7ma current on ldx pad 70 ld3 ld2 ld1 ld0 ld3_i ld2_i ld1_i ld0_i 1 st7scr 40/102 12 on-chip peripherals 12.1 watchdog timer (wdg) 12.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 12.1.2 main features n programmable timer (64 increments of 65536 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n hardware watchdog selectable by option byte n watchdog reset indicated by status flag 12.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 65,536 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 14 ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 14.watchdog timing (f cpu = 8 mhz) figure 25. watchdog block diagram cr register initial value wdg timeout period (ms) max ffh 524.288 min c0h 8.192 reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 65536 t1 t2 t3 t4 t5 1 st7scr 41/102 watchdog timer (contd) 12.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 12.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 12.1.6 low power modes wait instruction no effect on watchdog. halt instruction halt mode can be used when the watchdog is en- abled. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 514 cpu clocks. in the case of the software watchdog option, if a reset is gen- erated, the wdg is disabled (reset state). recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 12.1.7 interrupts none. 12.1.8 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 70 wdga t6 t5 t4 t3 t2 t1 t0 1 st7scr 42/102 12.2 time base unit (tbu) 12.2.1 introduction the timebase unit (tbu) can be used to generate periodic interrupts. 12.2.2 main features n 8-bit upcounter n programmable prescaler n period between interrupts: max. 8.1ms (at 8 mhz f cpu ) n maskable interrupt 12.2.3 functional description the tbu operates as a free-running upcounter. when the tcen bit in the tbucsr register is set by software, counting starts at the current value of the tbucv register. the tbucv register is incre- mented at the clock rate output from the prescaler selected by programming the pr[2:0] bits in the tbucsr register. when the counter rolls over from ffh to 00h, the ovf bit is set and an interrupt request is generat- ed if ite is set. the user can write a value at any time in the tbucv register. 12.2.4 programming example in this example, timer is required to generate an in- terrupt after a delay of 1 ms. assuming that f cpu is 8 mhz and a prescaler divi- sion factor of 256 will be programmed using the pr[2:0] bits in the tbucsr register, 1 ms = 32 tbu timer ticks. in this case, the initial value to be loaded in the tbucv must be (256-32) = 224 (e0h). ld a, e0h ld tbucv, a ; initialize counter value ld a 1fh ; ld tbucsr, a ; prescaler factor = 256, ; interrupt enable, ; tbu enable figure 26. tbu block diagram tbu 8-bit upcounter (tbucv register) interrupt request tbu prescaler f cpu tbucsr register pr1 pr0 pr2 tcen ite ovf msb lsb 0 0 1 tbu 0 1 st7scr 43/102 timebase unit (contd) 12.2.5 low power modes 12.2.6 interrupts note : the ovf interrupt event is connected to an interrupt vector (see interrupts chapter). it generates an interrupt if the ite bit is set in the tbucsr register and the i-bit in the cc register is reset (rim instruction). 12.2.7 register description tbu counter value register (tbucv) read/write reset value: 0000 0000 (00h) bits 7:0 = cv[7:0] counter value this register contains the 8-bit counter value which can be read and written anytime by soft- ware. it is continuously incremented by hardware if tcen=1. tbu control/status register (tbucsr) read/write reset value: 0000 0000 (00h) bits [7:6] = reserved. forced by hardware to 0 . bit 5 = ovf overflow flag this bit is set only by hardware, when the counter value rolls over from ffh to 00h. it is cleared by software reading the tbucsr register. writing to this bit does not change the bit value. 0: no overflow 1: counter overflow bit 4 = ite interrupt enabled. this bit is set and cleared by software. 0: overflow interrupt disabled 1: overflow interrupt enabled. an interrupt request is generated when ovf=1. bit 3 = tcen tbu enable. this bit is set and cleared by software. 0: tbu counter is frozen and the prescaler is reset. 1: tbu counter and prescaler running. bits 2:0 = pr[2:0] prescaler selection these bits are set and cleared by software to se- lect the prescaling factor. mode description wait no effect on tbu halt tbu halted. interrupt event event flag enable control bit exit from wait exit from halt counter over- flow event ovf ite yes no 70 cv7 cv6 cv5 cv4 cv3 cv2 cv1 cv0 70 0 0 ovf ite tcen pr2 pr1 pr0 pr2 pr1 pr0 prescaler division factor 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 1 st7scr 44/102 12.3 usb interface (usb) 12.3.1 introduction the usb interface implements a full-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and usb data buffer interface. no external com- ponents are needed apart from the external pull- up on usbdp for full speed recognition by the usb host. 12.3.2 main features n usb specification version 1.1 compliant n supports full-speed usb protocol n seven endpoints (including default endpoint) n crc generation/checking, nrzi encoding/ decoding and bit-stuffing n usb suspend/resume operations n on-chip 3.3v regulator n on-chip usb transceiver 12.3.3 functional description the block diagram in figure 27 , gives an overview of the usb interface hardware. for general information on the usb, refer to the universal serial bus specifications document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. data transfer to/from usb data buffer memory when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place to/from the usb data buffer. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 27. usb block diagram cpu transceiver 3.3v voltage regulator sie endpoint buffer usb address, and interrupts usbdm usbdp usbvcc 48 mhz registers registers data busses usbgnd buffer usb data interface 1 st7scr 45/102 usb interface (contd) usb endpoint ram buffers there are seven endpoints including one bidirec- tional control endpoint (endpoint 0), five in end- points (endpoint 1, 2, 3, 4, 5) and one out end- point (endpoint 2). endpoint 0 is 2 x 8 bytes in size, endpoint 1, 3, 4, and endpoint 5 are 8 bytes in size and endpoint 2 is 2 x 64 bytes in size . figure 28. endpoint buffer size endpoint 2 buffer out endpoint 1 buffer in endpoint 0 buffer in endpoint 0 buffer out endpoint 2 buffer in 8 bytes 8 bytes 8 bytes 64 bytes 64 bytes endpoint 3 buffer in 8 bytes endpoint 5 buffer in endpoint 4 buffer in 8 bytes 8 bytes 1 st7scr 46/102 usb interface (contd) 12.3.4 register description interrupt status register (usbistr) read/write reset value: 0000 0000 (00h) these bits cannot be set by software. when an in- terrupt occurs these bits are set by hardware. soft- ware must read them to determine the interrupt type and clear them after servicing. note: the ctr bit (which is an or of all the end- point ctr flags) cannot be cleared directly, only by clearing the ctr flags in the endpoint regis- ters. bit 7 = ctr correct transfer . this bit is set by hardware when a correct transfer operation is performed. this bit is an or of all ctr flags (ctr0 in the ep0r register and ctr_rx and ctr_tx in the epnrxr and ep- ntxr registers). by looking in the usbsr regis- ter, the type of transfer can be determined from the pid[1:0] bits for endpoint 0. for the other end- points, the endpoint number on which the transfer was made is identified by the ep[1:0] bits and the type of transfer by the in/out bit. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 6 = reserved, forced by hardware to 0. bit 5 = sovr setup overrun. this bit is set by hardware when a correct setup transfer operation is performed while the software is servicing an interrupt which occured on the same endpoint (ctr0 bit in the ep0r register is still set when setup correct transfer occurs). 0: no setup overrun detected 1: setup overrun detected when this event occurs, the usbsr register is not updated because the only source of the sovr event is the setup token reception on the control endpoint (ep0). bit 4 = err error . this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing, nonstandard framing or buffer overrun error detected note: refer to the err[2:0] bits in the usbsr register to determine the error type. bit 3 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb. the suspend request check is active immediately after each usb reset event and is disabled by hardware when suspend mode is forced (fsusp bit in the usbctlr register) until the end of resume sequence. bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0r, ep1rxr, ep1txr, ep2rxr and ep2txr registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardware when a sof token is re- ceived on the usb. 0: no sof received 1: sof received note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and, xor... 70 ctr 0 sovr error susp esusp reset sof 1 st7scr 47/102 usb interface (contd) interrupt mask register (usbimr) read/write reset value: 0000 0000 (00h) these bits are mask bits for all the interrupt condi- tion bits included in the usbistr register. when- ever one of the usbimr bits is set, if the corre- sponding usbistr bit is set, and the i- bit in the cc register is cleared, an interrupt request is gen- erated. for an explanation of each bit, please refer to the description of the usbistr register. control register (usbctlr) read/write reset value: 0000 0110 (06h) bit 7 = rsm resume detected this bit shows when a resume sequence has start- ed on the usb port, requesting the usb interface to wake-up from suspend state. it can be used to determine the cause of an esusp event. 0: no resume sequence detected on usb 1: resume sequence detected on usb bit 6 = usb_rst usb reset detected . this bit shows that a reset sequence has started on the usb. it can be used to determine the cause of an esusp event (reset sequence). 0: no reset sequence detected on usb 1: reset sequence detected on usb bits [5:4] = reserved, forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be put in halt mode to reduce power consumption. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset state until software clears this bit, at which point a usb-reset in- terrupt will be generated if enabled. 70 ctrm 0 sovr m errm susp m esusp m reset m sofm 70 rsm usb_ rst 00 resu me pdwn fsusp fres 1 st7scr 48/102 usb interface (contd) device address register (daddr) read/write reset value: 0000 0000 (00h) bit 7 = reserved, forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received or forced through bit fres in the us- bctlr register. usb status register (usbsr) read only reset value: 0000 0000 (00h) bits 7:6 = pid[1:0] token pid bits 1 & 0 for end- point 0 control . usb token pids are encoded in four bits. pid[1:0] correspond to the most significant bits of the pid field of the last token pid received by endpoint 0. note: the least significant pid bits have a fixed value of 01. when a ctr interrupt occurs on endpoint 0 (see register usbistr) the software should read the pid[1:0] bits to retrieve the pid name of the token received. the usb specification defines pid bits as: bit 5 = in/out last transaction direction for end- point 1, 2 , 3, 4 or 5. this bit is set by hardware when a ctr interrupt occurs on endpoint 1, 2, 3, 4 or 5. 0: out transaction 1: in transaction bits 4:3 = reserved, forced by hardware to 0. bits 2:0 = ep[2:0] endpoint number. these bits identify the endpoint which required at- tention. 000 = endpoint 0 001 = endpoint 1 010 = endpoint 2 011 = endpoint 3 100 = endpoint 4 101 = endpoint 5 error status register (errsr) read only reset value: 0000 0000 (00h) bits 7:3 = reserved, forced by hardware to 0. bits 2:0 = err[2:0] error type . these bits identify the type of error which oc- curred. note: these bits are set by hardware when an er- ror interrupt occurs and are reset automatically when the error bit (usbistr bit 4) is cleared by software. 70 0 add6add5add4add3add2add1add0 70 pid1 pid0 in/ out 0 0 ep2 ep1 ep0 pid1 pid0 pid name 00 out 10 in 1 1 setup 70 00000err2err1err0 err2 err1 err0 meaning 0 0 0 no error 0 0 1 bitstuffing error 0 1 0 crc error 011 eop error (unexpected end of packet or se0 not followed by j-state) 100 pid error (pid encoding error, unexpected or unknown pid) 101 memory over / underrun (mem- ory controller has not an- swered in time to a memory data request) 111 other error (wrong packet, timeout error) 1 st7scr 49/102 usb interface (contd) endpoint 0 register (ep0r) read/write reset value: 0000 0000(00h) this register is used for controlling endpoint 0. bits 6:4 and bits 2:0 are also reset by a usb reset, either received from the usb or forced through the fres bit in usbctlr. bit 7 = ctr0 correct transfer . this bit is set by hardware when a correct transfer operation is performed on endpoint 0. this bit must be cleared after the corresponding interrupt has been serviced. 0: no ctr on endpoint 0 1: correct transfer on endpoint 0 bit 6 = dtog_tx data toggle, for transmission transfers . it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware on recep- tion of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx are normally updated by hardware, on receipt of a relevant pid. they can be also written by the user, both for testing purposes and to force a specific (data0 or data1) token. bits 5:4 = stat_tx [1:0] status bits, for transmis- sion transfers . these bits contain the information about the end- point status, which are listed below table 15. transmission status encoding these bits are written by software. hardware sets the stat_tx and stat_rx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted. bit 3 = reserved, forced by hardware to 0. bit 2 = dtog_rx data toggle, for reception transfers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by hardware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. 70 ctr0 dtog _tx stat_ tx1 stat_ tx0 0 dtog _rx stat_ rx1 stat_ rx0 stat_tx1 stat_tx0 meaning 00 disabled: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is enabled (if an address match occurs, the usb interface handles the transaction). 1 st7scr 50/102 usb interface (contd) bits 1:0 = stat_rx [1:0] status bits, for reception transfers . these bits contain the information about the end- point status, which are listed below: table 16. reception status encoding these bits are written by software. hardware sets the stat_rx and stat_tx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint, so the software has the time to ex- amine the received data before acknowledging a new transaction. note 1: if a setup transaction is received while the status is different from disabled, it is acknowleded and the two directional status bits are set to nak by hardware. note 2: when a stall is answered by the usb device, the two directional status bits are set to stall by hardware. endpoint transmission register (ep1txr, ep2txr, ep3txr, ep4txr, ep5txr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 1, 2, 3, 4 or 5 transmission. bits 2:0 are also reset by a usb reset, either received from the usb or forced through the fres bit in the usbctlr register. bits [7:4] = reserved, forced by hardware to 0. bit 3 = ctr_tx correct transmission transfer . this bit is set by hardware when a correct transfer operation is performed in transmission. this bit must be cleared after the corresponding interrupt has been serviced. 0: no ctr in transmission on endpoint 1, 2, 3, 4 or 5 1: correct transfer in transmission on endpoint 1, 2, 3, 4 or 5 bit 2 = dtog_tx data toggle, for transmission transfers . this bit contains the required value of the toggle bit (0=data0, 1=data1) for the next data packet. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and dtog_rx are normally updated by hardware, at the receipt of a relevant pid. they can be also written by the user, both for testing purposes and to force a specific (data0 or data1) token. bits [1:0] = stat_tx [1:0] status bits, for trans- mission transfers . these bits contain the information about the end- point status, which is listed below table 17. transmission status encoding these bits are written by software, but hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint. this allows software to prepare the next set of data to be transmitted. stat_rx1 stat_rx0 meaning 00 disabled: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 stall: the endpoint is stalled and all reception requests re- sult in a stall handshake. 10 nak : the endpoint is naked and all reception requests re- sult in a nak handshake. 11 valid : this endpoint is ena- bled (if an address match oc- curs, the usb interface handles the transaction). 70 0000 ctr_t x dtog _tx stat_ tx1 stat_ tx0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission. 1 st7scr 51/102 usb interface (contd) endpoint 2 reception register (ep2rxr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 2 re- ception. bits 2:0 are also reset by a usb reset, ei- ther received from the usb or forced through the fres bit in the usbctlr register. bits [7:4] = reserved, forced by hardware to 0. bit 3 = ctr_rx reception correct transfer . this bit is set by hardware when a correct transfer operation is performed in reception. this bit must be cleared after that the corresponding interrupt has been serviced. bit 2 = dtog_rx data toggle, for reception transfers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. the receiver toggles dtog_rx only if it receives acorrect data packet and the packets data pid matches the receiver sequence bit. bits [1:0] = stat_rx [1:0] status bits, for recep- tion transfers . these bits contain the information about the end- point status, which is listed below: table 18. reception status encoding these bits are written by software, but hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. 70 0000 ctr_r x dtog _rx stat_ rx1 stat_ rx0 stat_rx1 stat_rx0 meaning 00 disabled: reception trans- fers cannot be executed. 01 stall: the endpoint is stalled and all reception requests re- sult in a stall handshake. 10 nak : the endpoint is naked and all reception requests re- sult in a nak handshake. 11 valid : this endpoint is ena- bled for reception. 1 st7scr 52/102 usb interface (contd) reception counter register (cnt0rxr) read/write reset value: 0000 0000 (00h) this register contains the allocated buffer size for endpoint 0 reception, setting the maximum number of bytes the related endpoint can receive with the next out or setup transaction. at the end of a reception, the value of this register is the max size decremented by the number of bytes re- ceived (to determine the number of bytes re- ceived, the software must subtract the content of this register from the allocated buffer size). transmission counter register (cnt0txr, cnt1txr, cnt3txr, cnt4txr, cnt5txr) read/write reset value 0000 0000 (00h) this register contains the number of bytes to be transmitted by endpoint 0, 1, 3, 4 or 5 at the next in token addressed to it. reception counter register (cnt2rxr) read/write reset value: 0000 0000 (00h) this register contains the allocated buffer size for endpoint 2 reception, setting the maximum number of bytes the related endpoint can receive with the next out transaction. at the end of a re- ception, the value of this register is the max size decremented by the number of bytes received (to determine the number of bytes received, the soft- ware must subtract the content of this register from the allocated buffer size). transmission counter register (cnt2txr) read/write reset value 0000 0000 (00h) this register contains the number of bytes to be transmitted by endpoint 2 at the next in token ad- dressed to it. 70 0 0 0 0 cnt3 cnt2 cnt1 cnt0 70 0 0 0 0 cnt3 cnt2 cnt1 cnt0 70 0 cnt6 cnt5 cnt4 cnt3 cnt2 cnt cnt0 70 0 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 1 st7scr 53/102 usb interface (contd) table 19. usb register map and reset values address (hex.) register name 76543210 20 usbistr reset value ctr 0 0 0 sovr 0 err 0 susp 0 esusp 0 reset 0 sof 0 21 usbimr reset value ctrm 0 0 0 sovrm 0 errm 0 suspm 0 esuspm 0 resetm 0 sofm 0 22 usbctlr reset value rsm 0 usb_rst 0 00 resume 0 pdwn 1 fsusp 1 fres 0 23 daddr reset value 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 24 usbsr reset value pid1 0 pid0 0 in /out 0 00 ep2 0 ep1 0 ep0 0 25 ep0r reset value ctr0 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 0 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 26 cnt0rxr reset value 00 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 27 cnt0txr reset value 00 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 ep1txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 29 cnt1txr reset value 00 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 2a ep2rxr reset value 00 0 0 ctr_rx 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 2b cnt2rxr reset value 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 2c ep2txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 2d cnt2txr reset value 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 2e ep3txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 2f cnt3txr reset value 00 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 30 ep4txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 31 cnt4txr reset value 00 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 32 ep5txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 1 st7scr 54/102 33 cnt5txr 0 0 0 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 34 errsr 0 0 0 0 0 err2 0 err1 0 err0 0 address (hex.) register name 76543210 1 st7scr 55/102 12.4 smartcard interface (crd) 12.4.1 introduction the smartcard interface (crd) provides all the re- quired signals for acting as a smartcard interface device. the interface is electrically compatible with (and certifiable to) the iso7816, emv, gsm and whql standards. both synchronous (e.g. memory cards) and asyn- chronous smartcards (e.g. microprocessor cards) are supported. the crd generates the required voltages to be applied to the smartcard lines. the power-off sequence is managed by the crd. card insertion or card removal is detected by the crd using a card presence switch connected to the external crddet pin. if a card is removed, the crd automatically deactivates the smartcard us- ing the iso7816 deactivation sequence. an maskable interrupt is generated when a card is inserted or removed. any malfunction is reported to the microcontroller via the smartcard interrupt pending register (crdipr) and smartcard status (crdsr) regis- ters. 12.4.2 main features n support for iso 7816-3 standard n character mode n 1 transmit buffer and 1 receive buffer n 4-mhz fixed card clock n 11-bit etu (elementary time unit) counter n 9-bit guardtime counter n 24-bit general purpose waiting time counter n parity generation and checking n automatic character repetition on parity error detection in transmission mode n automatic retry on parity error detection in reception mode n card power-off deactivation sequence generation n manual mode for driving the card i/o directly for synchronous protocols 12.4.3 functional description figure 29 gives an overview of the smartcard inter- face. figure 29. smartcard interface block diagram clk sel crd clk crdccr io crd crd crd rst vcc c8 crd c4 crd crdio crdc4 crdc8 crdrst crdclk crddet 0 1 uart shift register crdrxb crdtxb uart receive buffer uart transmit buffer card detection card insertion/ crdvcc power-off logic clock control uart bit 11-bit 4 mhz etu counter 9-bit guardtime counter 24-bit waiting time counter parity generation/checking communications control crd interrupt logic removal interrupt 1 st7scr 56/102 smartcard interface (contd) 12.4.3.1 power supply management smartcard power supply selection the smartcard interface consists of a power sup- ply output on the crdvcc pin and a set of card in- terface i/os which are powered by the same rail. the card voltage (crdvcc) is user programma- ble via the vcard [1:0] bits in the crdcr regis- ter (refer to the smartcard interface section). four voltage values can be selected: 5v, 3 v, 1.8 v or 0v. current overload detection and card removal for each voltage, when an overload current is de- tected (refer to section 12.4 on page 55 ), or when a card is removed, the crdvcc power supply output is directly connected to ground. 12.4.3.2 i/o driving modes smartcard i/os are driven in two principal modes: C uart mode (i.e. when the uart bit of the crdcr register is set) C manual mode, driven directly by software using the smartcard contact register (i.e. when the uart bit of the crdcr register is reset). card power-on activation must driven by software . card deactivation is handled automatically by the power-off functional state machine hardware. 12.4.3.3 uart mode two registers are connected to the uart shift register: crdtxb for transmission and crdrxb for reception. they act as buffers to off-load the cpu. a parity checker and generator is coupled to the shifter. character repetition and retry are supported. the uart is in reception mode by default and switches automatically to transmission mode when a byte is written in the buffer. priority is given to transmission. elementary time unit counter this 11-bit counter controls the working frequency of the uart. the operating frequency of the clock is the same as the card clock frequency (i.e. 4 mhz). a compensation mode can be activated via the comp bit of the crdetu1 register to allow a fre- quency granularity down to a half-etu. note: the decimal value is limited to a half clock cycle. the bit duration is not fixed. it alternates be- tween n clock cycles and n-1 clock cycles, where n is the value to be written in the crdetu register. the character duration (10 bits) is also equal to 10*(n - ?) clock cycles this is precise enough to obtain the character duration specified by the iso7816-3 standard. for example, if f=372 and d=32 (f being the clock rate conversion factor and d the baud rate adjust- ment), then etu =11.625 clock cycles. to achieve this clock rate, compensation mode must be activated and the etu duration must be programmed to 12 clock cycles. the result will be an average character duration of 11.5 clock cycles (for 10 bits). see figure 30 . guardtime counter the guardtime counter is a 9-bit counter which manages the character frame. it controls the dura- tion between two consecutive characters in trans- mission. it is incremented at the etu rate. no guardtime is inserted for the first character transmitted. the guardtime between the last byte received from the card and the next byte transmitted by the reader must be handled by software. 1 st7scr 57/102 figure 30. compensation mode 12cy 11cy 12cy 11cy 12cy 11cy 12cy 11cy 12cy 11cy start bit data bits parity bit uart crdio working clock f=372 d= 32 1 st7scr 58/102 smartcard interface (contd) waiting time counter the waiting time counter is a 24-bit counter used to generate a timeout signal. the elementary time unit counter acts as a pres- caler to the waiting time counter which is incre- mented at the etu rate. the waiting time counter can be used in both uart mode and manual mode and acts in differ- ent ways depending on the selected mode. the crdwt2, crdwt1 and crdwt0 are load registers only, the counter itself is not directly ac- cessible. uart mode the load conditions are either: C a start bit is detected while uart bit =1 and the wten bit =1. or C a write access to the crdwt2 register is per- formed while the uart bit = 1 and the wten bit = 0. in this case, the waiting time counter can be used as a general purpose timer. in uart mode, if the wten bit of the crdcr reg- ister is set, the counter is loaded automatically on start bit detection. software can change the time out value on-the-fly by writing to the crdwt registers. for example, in t=1 mode, software must load the block waiting time (bwt) time-out in the crdwt registers before the start bit of the last transmitted character. then, after transmission of this last character, sig- nalled by the txc interrupt, software must write the cwt value (character waiting time) in the crdwt registers. see example in figure 31 . manual mode the load conditions are: C a write access to the crdwt2 register is per- formed while the uart bit = 0 and the wten bit = 0 in manual mode, if the wten bit of the crdcr register is reset, the timer acts as a general pur- pose timer. the timer is loaded when a write ac- cess to the crdwt2 register occurs. the timer starts when the wten bit = 1. 12.4.3.4 interrupt generator the smartcard interface has 2 interrupt vectors: C card insertion/removal interrupt C crd interrupt the crd interrupt is cleared when software reads the crdipr register. the card insertion/removal is an external interrupt and is cleared automatical- ly by hardware at the end of the interrupt service routine (iret instruction). if an interrupt occurs while the crdipr register is being read, the corresponding bit will be set by hardware after the read access is done. figure 31. waiting time counter example bwt cwt reader smartcard firmware must program bwt firmware must program cwt txc interrupt start bit waiting time counter loaded on start bit char0 char1 charn char0 char1 1 st7scr 59/102 smartcard interface (contd) 12.4.3.5 card detection mechanism the crddet bit in the crdcr register indicates if the card presence detector (card switch) is open or closed when a card is inserted. when the crdirf bit of the crdsr is set, it indicates that a card is present. to be able to power-on the smartcard, card pres- ence is mandatory. removing the smartcard will automatically start the iso7816-3 card deactiva- tion sequence (see section 12.4.3.6 ). there is no hardware debouncing: the crdirf bit changes whenever the level on the crddet pin changes. the card switch can generate an in- terrupt which can be used to wake up the device from suspend mode and for software debouncing. three different cases can occur: C the microcontroller is in run mode, waiting for card insertion: card insertion generates an interrupt and the crdirf bit in the crdsr register is set. de- bouncing is managed by software. after the time required for debouncing, if the crdirf bit is set, the crdvcc bit in the crdcr register is set by software to apply the selected voltage to the crdvcc pin C the microcontroller is in suspend mode and a card is inserted: the st7 is woken up by the interrupt . the card insertion is then handled in the same way as in the previous case. C the card is removed: C the crdirf bit is reset without hardware de- bouncing C a card insertion/removal interrupt is generat- ed, (if enabled by the crdirm bit in the miscr2 register) C the crdvcc bit is immediately reset by hardware, starting the card deactivation se- quence. figure 32. card detection block diagram crddet crd crdsr 1 0 card insertion/removal 0 7 irf det crdcr 0 7 cnf crd miscr2 0 7 irm pull-up edge detector interrupt request smartcard interface (crd) 1 st7scr 60/102 smartcard interface (contd) 12.4.3.6 card deactivation sequence this sequence can be activated in two different ways: C automatically as soon as the card presence de- tector detects a card removal (via the crdirf bit in the crdsr register, refer to section 12.4.3.5 ). C by software, writing the crdvcc bit in the crd- cr register, for example: C if there is a smartcard current overflow (i.e. when the iovff bit in the crdsr register is set) C if the voltage is not within the specified range (i.e. when the vcardok bit in the crdsr register is cleared), but software must clear the crdvcc bit in the crdccr register to start the deactivation sequence. when the crdvcc bit is cleared, this starts the deactivation sequence. crdclk, crdio, crdc4 and crdc8 pins are then deactivated as shown in figure 33 : figure 33. card deactivation sequence figure 34. card voltage selection and power off block diagram crdvcc pin crdrst pin crdclk pin crdio pin crdc4 pin crdc8 pin 8 cpu clk cycles crdvcc crd crdccr block 0 7 vcc crdcr 0 7 irf crdsr 0 7 crd vcard 1 power off iovf ok crdier 0 7 crdipr 0 7 iovp vcrd smartcard power supply block 5v vcardok interrupt request iovf interrupt request 2 2 card voltage selection 2 iovm vcrd p m vcard 0 vcard 1 st7scr 61/102 smartcard interface (contd) figure 35. power off timing diagram note: refer to the electrical characteristics sec- tion for the values of t on and t off . figure 36. card clock selection block diagram 11 00 00 vcard[1:0] crdvcc vcardok vcrdp interrupt v cardok 11 vcrdp interrupt software power-off voltage error power-on power-on t off t on t on t off 0.4v clk 4 mhz 1 0 sel crd clk crdccr power off block crdclk isoclk div pll pll osc 4 mhz 1 st7scr 62/102 smartcard interface (contd) 12.4.4 register description smartcard interface control regis- ter (crdcr) read/write reset value: 0000 0000 (00h) bit 7 = crdrst smartcard interface reset. this bit is set by software to reset the uart of the smartcard interface. 0: no smartcard uart reset 1: smartcard uart reset bit 6 = crddet card presence detector. this bit is set and cleared by software to configure the card presence detector switch. 0: switch open if no card is present 1: switch closed if no card is present bits [5:4] = vcard[1:0] card voltage selection. these bits select the card voltage. bit 3 = uart uart mode selection. this bit is set and cleared by software to select uart or manual mode. 0: crdio pin is a copy of the crdio bit in the crdccr register (manual mode). 1: crdio pin is the output of the smartcard uart (uart mode). caution: before switching from manual mode to uart mode, software must set the crdio bit in the crdccr register. bit 2 = wten waiting time counter enable. 0: waiting time counter stopped. while wten = 0, a write access to the crdwt2 register loads the waiting time counter with the load value held in the crdwt0, crdwt1 and crdwt2 regis- ters. 1: start counter. in uart mode, the counter is au- tomatically reloaded on start bit detection. bit 1 = crep automatic character repetition in case of parity error. 0: in reception mode: no parity error signal indica- tion (no retry on parity error). in transmission mode: no error signal process- ing. no retransmission of a refused character on parity error. 1: automatic parity management: in transmission mode: up to 4 character repeti- tions on parity error. in reception mode: up to 4 retries are made on parity error. the parf parity error flag is set by hardware if a parity error is detected. if the transmitted character is refused, the parf bit is set (but the txcf bit is reset) and an interrupt is generated if the parm bit is set. note: if crep=1, the parf flag is set at the 5th error (after 4 character repetitions or 4 retries). if crep=0, the parf bit is set after the first parity error. bit 0 = conv iso convention selection. 0: direct convention, the b0 bit (lsb) is sent first, a 1 is a level 1 on the card i/o pin, the parity bit is added after the b7 bit. 1: inverse convention, the b7 bit (msb) is sent first, a 1 is a level 0 on card i/o pin, the parity bit is added after the b0 bit. note: to detect the convention used by any card, apply the following rule. if a card uses the conven- tion selected by the reader, an rxc event occurs at answer to reset. otherwise a parity error also occurs. 70 crd rst crd det vcar d 1 vcar d 0 u art wt en c rep co nv bit 1 bit 0 vcard 00 0v 0 1 1.8v 10 3v 11 5v 1 st7scr 63/102 smartcard interface (contd) smartcard interface status register (crdsr) read only (read/write on some bits) reset value: 1000 0000 (80h) bit 7 = txbef transmit buffer empty flag. - read only 0: transmit buffer is not empty 1: transmit buffer is empty bit 6 = crdirf card insertion/removal flag. - read only 0: no card is present 1: a card is present bit 5 = iovf card overload current flag. - read only 0: no card overload current 1: card overload current bit 4 = vcardok card voltage status flag. - read only 0: the card voltage is not in the specified range 1: the card voltage is within the specified range bit 3 = wtf waiting time counter overflow flag. - read only 0: the wt counter has not reached its maximum value 1: the wt counter has reached its maximum val- ue bit 2 = txcf transmitted character flag. - read/write this bit is set by hardware and cleared by soft- ware. 0: no character transmitted 1: a character has been transmitted bit 1 = rxcf received character flag. - read only this bit is set by hardware and cleared by hard- ware when the crdrxb buffer is read. 0: no character received 1: a character has been received bit 0 = parf parity error flag. - read/write this bit is set by hardware and cleared by soft- ware. 0: no parity error 1: parity error note: when a character is received, the rxcf bit is always set.when a character is received with a parity error, the parf bit is also set. 70 txbe f crd irf iovf vcard ok wtf txc f rxc f par f st7scr 64/102 smartcard interface (contd) smartcard contact control register (crdccr) read/write reset value: 00xx xx00 (xxh) note: to modify the content of this register, the ld instruction must be used (do not use the bset and bres instructions). bit 7 = clksel card clock selection. this bit is set and cleared by software. 0: the signal on the crdclk pin is a copy of the crdclk bit. 1: the signal on the crdclk pin is a 4mhz fre- quency clock. note: t o start the clock at a known level, the crd- clk bit should be changed before the cl ksel bit. bit 6 = reserved, must be kept cleared. bit 5 = crdc8 crdc8 pin control. reading this bit returns the value present on the crdc8 pin. writing this bit outputs the bit value on the pin. bit 4 = crdc4 crdc4 pin control reading this bit returns the value present on the crdc4 pin. writing this bit outputs the bit value on the pin. bit 3 = crdio crdio pin control . this bit is active only if the uart bit in the crdcr register is reset. reading this bit returns the value present on the crdio pin. if the uart bit is reset: C writing 0 forces a low level on the crdio pin C writing 1 forces the crdio pin to open drain hi-z. bit 2 = crdclk crdclk pin control this bit is active only if the clksel bit of the crd- ccr register is reset. reading this bit returns the value present in the register (not the crdclk pin value). when the clksel bit is reset: 0: level 0 to be applied on crdclk pin. 1: level 1 to be applied on crdclk pin. note: to ensure that the clock stops at a given value, write the desired value in the crdclk bit prior to changing the cl ksel bit from 1 to 0. bit 1 = crdrst crdrst pin control. reading this bit returns the value present on the crdrst pin. writing this bit outputs the bit value on the pin. bit 0 = crdvcc crdvcc pin control. this bit is set and cleared by software and forced to 0 by hardware when no card is present (crdirf bit=0). 0: no voltage to be applied on the crdvcc pin. 1: the selected voltage must be applied on the crdvcc pin. figure 37. smartcard i/o pin structure 70 clk sel - crd c8 crd c4 crd io crd clk crd rst crd vcc i/o pin data bus crdccr register st7scr 65/102 smartcard interface (contd) smartcard elementary time unit reg- ister (crdetux) crdetu1 read/write reset value: 0000 0001 (01h) bit 7 = comp elementary time unit compensa- tion. 0: compensation mode disabled. 1: compensation mode enabled. to allow non in- teger value, one clock cycle is subtracted from the etu value on odd bits. see figure 30 . bit [6:3] = reserved bits 2:0 = etu [10:8] etu value in card clock cy- cles. writing crdetu1 register reloads the etu coun- ter. crdetu0 read/write reset value: 0111 0100 (74h) bits 7:0 = etu [7:0] etu value in card clock cy- cles. note: the value of etu [10:0] must in the range 12 to 2047. to write 2048, clear all the bits. guardtime register (crdgtx) crdgt1 read/write reset value: 0000 0000 (00h) crdgt0 read/write reset value: 0000 1100 (0ch) software writes the guardtime value in this regis- ter. the value is loaded at the end of the current guard period. gt: guard time: minimum time between two con- secutive start bits in transmission mode. value ex- pressed in elementary time units (from 11 to 511). the guardtime between the last byte received from the card and the next byte transmitted by the reader must be handled by software. 70 comp0000etu10etu9etu8 70 etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 70 0000000gt8 70 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 st7scr 66/102 smartcard interface (contd) character waiting time register (crd- wtx) crdwt2 read/write reset value: 0000 0000 (00h) . crdwt1 read/write reset value: 0010 0101 (25h) crdwt0 read/write reset value: 1000 0000 (80h) wt: character waiting time value expressed in etu (0 / 16777215). the crdwt0, crdwt1 and crdwt2 registers hold the load value of the waiting time counter. note: a read operation does not return the counter value. this counter can be used as a general purpose timer. if the wten bit of the crdcr register is reset, the counter is reloaded when a write access in the crdwt2 register occurs. it starts when the wten bit is set. if the wten bit in the crdcr register is set and if uart mode is activated, the counter acts as an autoreload timer. the timer is reloaded when a start bit is sent or detected. an interrupt is generat- ed if the timer overflows between two consecutive start bits. note: when loaded with a 0 value, the waiting time counter stays at 0 and the wtf bit = 1. 70 wt 23 wt 22 wt 21 wt 20 wt 19 wt 18 wt 17 wt 16 70 wt 15 wt 14 wt 13 wt 12 wt 11 wt 10 wt9 wt8 70 wt 7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 st7scr 67/102 smartcard interface (contd) smartcard interrupt enable register (crdier) read/write reset value: 0000 0000 (00h) bit 7 = txbem transmit buffer empty interrupt mask. this bit is set and cleared by software to enable or disable the txbe interrupt. 0: txbe interrupt disabled 1: txbe interrupt enabled bit 6 = reserved. bit 5 = iovfm card overload current interrupt mask. this bit is set and cleared by software to enable or disable the iovf interrupt. 0: iovf interrupt disabled 1: iovf interrupt enabled bit 4= vcrdm card voltage error interrupt mask. this bit is set and cleared by software to enable or disable the vcrd interrupt. 0: vcrd interrupt disabled 1: vcrd interrupt enabled bit 3 = wtm waiting timer interrupt mask. this bit is set and cleared by software to enable or disable the waiting timer overflow interrupt. 0: wt interrupt disabled 1: wt interrupt enabled bit 2 = txcm transmitted character interrupt mask this bit is set and cleared by software to enable or disable the txc interrupt. 0: txc interrupt disabled 1: txc interrupt enabled bit 1 = rxcm received character interrupt mask this bit is set and cleared by software to enable or disable the rxc interrupt. 0: rxc interrupt disabled 1: rxc interrupt enabled bit 0 = parm parity error interrupt. mask this bit is set and cleared by software to enable or disable the parity error interrupt for parity error. 0: par interrupt disabled 1: par error interrupt enabled 70 txbe m -iovf m vcrdm wtm txc m rxc m par m st7scr 68/102 smartcard interface (contd) smartcard interrupt pending regis- ter (crdipr) read only reset value: 0000 0000 (00h) this register indicates the interrupt source. it is cleared after a read operation. bit 7 = txbep transmit buffer empty interrupt pending. this bit is set by hardware when a t xbe event oc- curs and the txbem bit is set. 0: no txbe interrupt p ending 1: txbe interrupt pending bit 6 = reserved. bit 5 = iovf card overload current interrupt pending. this bit is set by hardware when a iovf event oc- curs and the iovfm bit is set. 0: no iovf interrupt pending 1: iovf interrupt pending bit 4 = vcrdp card voltage error interrupt pend- ing. this bit is set by hardware when the vcardok bit goes from 1 to 0 while the vcrdm bit is set. 0: no vcrd interrupt pending. 1: vcrd interrupt pending. bit 3 = wtp waiting timer overflow interrupt pending. this bit is set by hardware when a wtp event oc- curs and the wtpm bit is set. 0: no wt interrupt pending 1: wt interrupt pending bit 2 = txcp transmitted character interrupt pending. this bit is set by hardware when a character is transmitted and the txcm bit is set. it indicates that the crdtxb buffer can be loaded with the next character to be transmitted. 0: no txc interrupt pending 1: txc interrupt pending bit 1 = rxcp received character interrupt pend- ing. this bit is set by hardware when a character is re- ceived and the rxcm bit is set. it indicates that the crdrxb buffer can be read. 0: no rxc interrupt pending 1: rxc interrupt pending bit 0 = parp parity error interrupt pending. this bit is set by hardware when a par event oc- curs and the parm bit is set. 0: no par interrupt pending 1: par interrupt pending smartcard transmit buffer (crdtxb) read/write reset value: 0000 0000 (00h) this register is used to send a byte to the smart- card. smartcard receive buffer (crdrxb) read reset value: 0000 0000 (00h) this register is used to receive a byte from the smartcard. 70 txbe p -iovf p vcrd p wtp txcp rxc p par p 70 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 70 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 st7scr 69/102 smartcard interface (contd) table 20. register map and reset values address (hex.) register label 7654321 0 00 crdcr reset value crdrst 0 detcnf 0 vcard1 0 vcard0 0 uart 0 wten 0 crep 0 conv 0 01 crdsr reset value txbef 1 crdirf 0 iovf 0 vcardok 0 wtf 0 txcf 0 rxcf 0 parf 0 02 crdccr reset value clksel 0 - 0 crdc8 x crdc4 x crdio x crdclk 0 crdrst x crdvcc 0 03 crdetu1 reset value comp 0 - 0 - 0 - 0 - 0 etu10 1 etu9 0 etu8 0 04 crdetu0 reset value etu7 0 etu6 1 etu5 1 etu4 1 etu3 0 etu2 1 etu1 0 etu0 0 05 crdgt1 reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 gt8 0 06 crdgt0 reset value gt7 0 gt6 0 gt5 0 gt4 0 gt3 1 gt2 1 gt1 0 gt0 0 07 crdwt2 reset value wt23 0 wt22 0 wt21 0 wt20 0 wt19 0 wt18 0 wt17 0 wt16 0 08 crdwt1 reset value wt15 0 wt14 0 wt13 1 wt12 0 wt11 0 wt10 1 wt9 0 wt8 1 09 crdwt0 reset value wt7 1 wt6 0 wt5 0 wt4 0 wt3 0 wt2 0 wt1 0 wt0 0 0a crdier reset value txbem 0 - 0 iovm 0 vcrdm 0 wtm 0 txcm 0 rxcm 0 parm 0 0b crdipr reset value txbep 0 - 0 iovp 0 vcrdp wtp 0 txcp 0 rxcp 0 parp 0 0c crdtxb reset value tb7 0 tb6 0 tb5 0 tb4 0 tb3 0 tb2 0 tb1 0 tb0 0 0d crdrxb reset value rb7 0 rb6 0 rb5 0 rb4 0 rb3 0 rb2 0 rb1 0 rb0 0 st7scr 70/102 13 instruction set 13.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 21. st7 addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 st7scr 71/102 instruction set overview (contd) 13.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 13.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 13.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 13.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 13.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st7scr 72/102 instruction set overview (contd) 13.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 22. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 13.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative st7scr 73/102 instruction set overview (contd) 13.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf st7scr 74/102 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st7scr 75/102 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z st7scr 76/102 14 electrical characteristics 14.1 absolute maximum ratings this product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid appying any voltage higher than the spec- ified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =ta + pd x rthja where: t a = ambient temperature. rthja =package thermal resistance (junction-to ambient). p d = p int + p port . p int =i dd x v dd (chip internal power). p port =port power dissipation determined by the user) stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these conditions is not implied. exposure to maximum rating for ex- tended periods may affect device reliability. general warning: direct connection to v dd or v ss of the i/o pins could damage the device in case of program counter corruption (due to unwanted change of the i/o configuration). to guarantee safe conditions, this connection has to be done through a typical 10k w pull-up or pull-down resistor. thermal characteristics symbol ratings value unit v dd - v ss supply voltage 6.0 v v in input voltage v ss - 0.3 to v dd + 0.3 v v out output voltage v ss - 0.3 to v dd + 0.3 v esd esd susceptibility 2000 v esdcard esd susceptibility for card pads 4000 v i vdd_i total current into v dd_i (source) 250 ma i vss_i total current out of v ss_i (sink) 250 symbol ratings value unit r thja package thermal resistance tqfp64 so24 60 80 c/w t jmax max. junction temperature 150 c t stg storage temperature range -65 to +150 c pd power dissipation (maximum value) 500 mw st7scr 77/102 14.2 recommended operating conditions (operating conditions t a = 0 to +70c unless otherwise specified) note 1: positive injection the i inj+ is done through protection diodes insulated from the substrate of the die. note 2: for smartcard i/os, v card has to be considered. note 3: negative injection C the i inj- is done through protection diodes not insulated from the substrate of the die. the draw- back is a small leakage (few a) induced inside the die when a negative injection is performed. this leak- age is tolerated by the digital structure, but it acts on the analog line according to the impedance versus a leakage current of few a (if the mcu has an ad converter). the effect depends on the pin which is submitted to the injection. of course, external digital signals applied to the component must have a max- imum impedance close to 50k w . location of the negative current injection: C pure digital pins can tolerate 1.6ma. in addition, the best choice is to inject the current as far as possible from the analog input pins. general note : when several inputs are submitted to a current injection, the maximum i inj is the sum of the positive (resp. negative) currrents (instantaneous values). general symbol parameter conditions min typ max unit v dd supply voltage 4.0 5.5 v f osc external clock source 4 mhz t a ambient temperature range 0 70 c current injection on i/o port and control pins symbol parameter conditions min typ max unit i inj+ total positive injected current (1) v external > v dd (standard i/os) v external > v sc_pwr (smartcard i/os) 20 ma i inj- total negative injected current (2,3) v external < v ss digital pins analog pins 20 ma st7scr 78/102 recommended operating conditions (contd) (t a =0 to +70 o c, v dd -v ss =5.5v unless otherwise specified) notes: 1. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss ; clock input (osc1) driven by external square wave. 2. all i/o pins in input mode with a static value at v dd or v ss ; clock input (osc1) driven by external square wave. t = 0... +70 o c, voltages are referred to v ss unless otherwise specified: note 1 : hysteresis voltage between schmitt trigger switching levels. based on characterisation results, not tested. note 2 : guaranteed by characterization symbol parameter conditions min typ. max unit i dd supply current in run mode 1) f osc = 4mhz 10 15 ma supply current in wait mode 2) 3ma supply current in suspend mode external i load = 0ma (usb transceiver enabled) 500 m a supply current in halt mode external i load = 0ma (usb transceiver disabled) 50 100 i/o port pins symbol parameter conditions min typ max unit v il input low level voltage 0.3xv dd v v ih input high level voltage 0.7xv dd v hys schmidt trigger voltage hysteresis 1) 400 mv v ol output low level voltage for standard i/o port pins i=-5ma 1.3 v i=-2ma 0.4 v oh output high level voltage i=3ma v dd -0.8 i l input leakage current v ss st7scr 79/102 14.3 supply and reset characteristics (t = 0 to +70 o c, v dd - v ss = 5.5v unless otherwise specified. 14.4 clock and timing characteristics 14.4.1 general timings (operating conditions t a = 0 to +70c unless otherwise specified) * d t inst is the number of t cpu to finish the current instruction execution. 14.4.2 external clock source low voltage detector and supervisor (lvds) symbol parameter conditions min typ max unit v it+ reset release threshold (v dd rising) 3.7 3.9 v v it- reset generation threshold (v dd falling) 3.3 3.5 v v hys hysteresis v it+ - v it- 200 mv v tpor v dd rise time rate 20 ms/v symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =4mhz 500 750 3000 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 10 22 t cpu f cpu =4mhz 2.5 5.5 m s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 38 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a st7scr 80/102 clock and timing characteristics (contd) figure 38. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. osc1 osc2 f osc external st7xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st7scr 81/102 clock and timing characteristics (contd) 14.4.3 crystal resonator oscillators the st7 internal clock is supplied with one crystal resonator oscillator. all the information given in this paragraph are based on characterization re- sults with specified typical external componants. in the application, the resonator and the load capaci- tors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crystal resonator manufacturer for more details (frequen- cy, package, accuracy...). figure 39. typical application with a crystal resonator notes: 1. resonator characteristics given by the crystal resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal resonator manufacturer for more details. symbol parameter conditions min typ max unit f osc oscillator frequency 3) mp: medium power oscillator 4 mhz r f feedback resistor 20 40 k w c l1 c l2 recommanded load capaci- tances versus equivalent se- rial resistance of the crystal resonator (r s ) see table 4 on page 20 (mp oscillator) 22 56 pf i 2 osc2 driving current v dd =5v v in =v ss (mp oscillator) 110 190 m a oscil. typical crystal resonator c l1 [pf] c l2 [pf] t su(osc) [ms] 2) reference freq. characteristic 1) crystal mp jauch ss3-400-30-30/30 4mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =60 w 33 34 7~10 osc2 osc1 f osc c l1 c l2 i 2 r f st7xxx resonator when resonator with integrated capacitors st7scr 82/102 14.5 memory characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. 14.5.1 ram and hardware registers 14.5.2 flash memory operating conditions: f cpu = 8 mhz. warning: do not connect 12v to v pp before v dd is powered on, as this may damage the device. 14.6 smartcard supply supervisor electrical characteristics (t a = 0... +70 o c, 4.0 < v dd - v ss < 5.5v unless otherwise specified) symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 2 v dual voltage flash memory symbol parameter conditions min typ max unit f cpu operating frequency read mode 8 mhz write / erase mode, t a =25c 8 v pp programming voltage 4.0v <= v dd <= 5.5v 11.4 12.6 v i pp v pp current write / erase 30 ma t prog byte programming time t a =25c 100 500 s t erase sector erasing time 2 10 sec device erasing time 5 10 t vpp internal v pp stabilization time 10 s t ret data retention t a 55c 20 years n rw write erase cycles t a =25c 100 cycles smartcard supply supervisor symbol parameter conditions min typ max unit 5v regulator output (for iec7816-3 class a cards) v card smartcard power supply voltage 4.6 5.00 5.4 v i sc smartcard supply current 55 ma i ovdet current overload detection 120 1) ma t idet detection time on current overload 170 1) 1400 1) s t off v card turn off time (see figure 35 on page 61 ) c loadmax 4.7uf 750 s t on v card turn on time (see figure 35 on page 61 ) c loadmax 4.7uf 150 500 s i vdd v dd supply current see note 100 ma 3v regulator output (for iec7816-3 class b cards) v card smartcard power supply voltage 2.7 3.3 v i sc smartcard supply current 50 ma i ovdet current overload detection 100 1) ma t idet detection time on current overload 170 1) 1400 1) us t off v card turn off time (see figure 35 on page 61 ) c loadmax 4.7uf 750 us st7scr 83/102 note 1 : guaranteed by design. note 2 : data based on characterization results, not tested in production. notes : v dd = 4.75 v, card consumption = 55ma, crdclk frequency = 4mhz, led with a 3ma current, usb in recep- tion mode and cpu in wfi mode. t on v card turn on time (see figure 35 on page 61 ) c loadmax 4.7uf 150 500 s 1.8v regulator output (for iec7816-3 class c cards) v card smartcard power supply voltage 1.65 1.95 v i sc smartcard supply current 20 ma i ovdet current overload detection 100 1) ma t idet detection time on current overload 170 1) 1400 1) us t off v card turn off time (see figure 35 on page 61 ) c loadmax 4.7uf 750 us t on v card turn on time (see figure 35 on page 61 ) c loadmax 4.7uf 150 500 s smartcard clkpin v ol output low level voltage i=-50ua - - 0.4 2) v v oh output high level voltage i=50ua v card -0.5 2) -- v t ohl output h-l fall time c l =30pf - 20 ns t olh output l-h rise time c l =30pf - 20 ns f var frequency variation - 1 % f duty duty cycle 45 55 % i sgnd short-circuit to ground 15 ma smartcard i/o pin v il input low level voltage - - 0.5 2) v v ih input high level voltage 0.6 v card 2) -- v v ol output low level voltage i=-0.5ma - - 0.4 2) v v oh output high level voltage i=20ua 0.8 v card 2) -v card 2) v i l input leakage current v ss st7scr 85/102 emc characteristics (contd) 14.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 14.7.2.1 electro-static discharge (esd) electro-static discharges (1 positive then 1 nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). the human body model is simulated. this test conforms to the jesd22-a114a stand- ard. see figure 40 and the following test sequenc- es. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. 14.7.2.2 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: C corrupted program counter C unexpected reset C critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device,over the range of spec- ification values.when unexpected behaviour is de- tected,the sofware can be hardened to prevent un- recoverable errors occurring (see application note an1015). absolute maximum ratings figure 40. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 1500 v st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator human body model st7scr 86/102 emc characteristics (contd) 14.7.2.3 static and dynamic latch-up n lu: 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu: electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 41 . for more details, refer to the an1181 st7 application note. electrical sensitivities figure 41. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss st7scr 87/102 emc characteristics (contd) 14.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 42 and figure 43 for standard pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 42. positive stress on a standard pad vs. v ss figure 43. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path st7scr 88/102 emc characteristics (contd) multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 44 is implemented to protect the device against esd. figure 44. multisupply configuration v dda v ssa v dda v dd v ss back to back diode between grounds v ssa st7scr 89/102 14.8 communication interface characteristics 14.8.1 usb - universal bus interface note 1: rl is the load connected on the usb drivers. note 2: all the voltages are measured from the local ground potential. figure 45. usb: data signal rise and fall time note1: measured from 10% to 90% of the data signal. for more detailed informations, please refer to chapter 7 (electrical) of the usb specification (version 1.1). usb dc electrical characteristics parameter symbol conditions min. max. unit input levels: differential input sensitivity vdi i(d+, d-) 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 v single ended receiver threshold vse 1.3 2.0 v output levels static output low vol rl of 1.5k ohms to 3.6v 0.3 v static output high voh rl of 15k ohm to v ss 2.8 3.6 v usbvcc: voltage level usbv v dd =5v 3.00 3.60 v usb: full speed electrical characteristics parameter symbol conditions min max unit driver characteristics: rise time tr note 1,cl=50 pf 4 20 ns fall time tf note 1, cl=50 pf 4 20 ns rise/ fall time matching trfm tr/tf 90 110 % output signal crossover voltage vcrs 1.3 2.0 v differential data lines v ss tf tr crossover points vcrs st7scr 90/102 15 package characteristics 15.1 package mechanical data figure 46. 64-pin thin quad flat package figure 47. 24-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 c h l l1 e b a a1 a2 e e1 d d1 dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.599 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 a 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 24 dim. mm inches min typ max min typ max c h x 45 l a a a1 e b d h e st7scr 91/102 figure 48. package mechanical data (contd) figure 49. recommended reflow oven profile (mid jedec) 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec st7scr 92/102 16 device configuration and ordering information each device is available for production in rom versions and in user programmable versions (high density flash). flash devices are shipped to customers with a default content (ffh). this implies that flash devices have to be con- figured by the customer using the option byte while the rom devices are factory-configured. 16.0.1 option bytes the 8 option bits from the flash are programmed through the static option byte sob1. the descrip- tion of each of these 8 bits is given below. static option byte (sob1) opt7:6 = reserved opt5= wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always activated) 1: software (watchdog to be activated by software) opt4 = nest interrupt controller this bit enables the nested interrupt controller. 0: nested interrupt controller disabled 1: nested interrupt controller enabled opt3 = isoclk clock source selection 0: card clock is generated by the divider (48mhz/ 12 = 4mhz). 1: card clock is generated by the oscillator. opt2 = retry number of retries for uart iso 0: in case of an erroneous transfer, character is transmitted 4 times. 1: in case of an erroneous transfer, character is transmitted 5 times. opt1 = reserved, must be kept at 1. opt0 = fmp_r flash memory read-out protec- tion this option indicates if the user flash memory is protected against read-out piracy. this protection is based on read and a write protection of the memory in test modes and icp mode. erasing the option bytes when the fmp_r option is selected induce the whole user memory erasing first. 0 : read-out protection enabled 1 : read-out protection disabled opt 7654321 opt 0 -- -- wdg- sw nest isoclk retry - fmp_r st7scr 93/102 16.1 device ordering information and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all un- used bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. see page 94 . the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 50. sales type coding rules table 23. ordering information note 1. /xxx stands for the rom or fastrom- code name assigned by stmicroelectronics. st7 f scr1 r4b1/xxx family version code sub family number of pins rom size code package type temperature code rom code (three letters) 1 = standard (0 to +70c) t = tqfp 4 = 16k r = 64 pins no letter = rom m = plastic so x = 24pins f = flash p = fastrom sales type 1) program memory (bytes) ram (bytes) package st7scr1r4t1/xxx 16k rom 768 tqfp64 st7pscr1r4t1/xxx 16k fastrom st7fscr1r4t1 16k flash st7scr1e4m1/xxx 16k rom so24 st7pscr1e4m1/xxx 16k fastrom st7fscr1e4m1 16k flash st7scr 94/102 st7scr microcontroller option list c ustomer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option): note: die product only for rom device special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: s024 (13 char. max) : _ _ _ _ _ _ _ _ tqfp64 (10 char. max) : _ _ _ _ _ _ _ _ _ _ watchdog: wdgsw [ ] software activation [ ] hardware activation nested interrupts nest [ ] nested interrupts [ ] non nested interrupts iso clock source isoclk [ ] oscillator [ ] divider no. of retries retry [ ] 5 [ ] 4 readout protection: fmp_r [ ] disabled [ ] enabled signature date -------------------------- rom device: -------------------------- | | ------------------------------------ 16k ------------------------------------ | | so24: | [ ] st7scr1e4m1 | tqfp64: | [ ] st7scr1r4t1 | -------------------------- fastrom device: -------------------------- | | ------------------------------------ 16k ------------------------------------ | | so24: | [ ] st7pscr1e4m1 | tqfp64: | [ ] st7pscr1r4t1 | ----------------------------------------------------------------- packaged product: ----------------------------------------------------------------- | | ---------------------------------------------------- die product (dice tested at 25c only) ---------------------------------------------------- [ ] tape & reel [ ] tray (tqfp package only) | [ ] tape & reel [ ] tube (so package only) | [ ] inked wafer | [ ] sawn wafer on sticky foil st7scr 95/102 16.2 development tools table 24. development tools 16.2.1 adaptor/socket proposal tbd development tool sales type remarks emulator st7mdts1-emu2b programming board st7mdts1-epb2 st7scr 96/102 16.3 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization st7scr 97/102 an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description st7scr 98/102 17 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 1.2 removed lvd option bit (lvd cannot be disabled) updated figure 7 on page 15 dec-01 1.3 changed status of the document changed table 1, device summary, on page 1 changed figure 4 on page 10 changed section 4.2 on page 14 added note in section 4.5 on page 15 changed description of the following registers in section 12.3.4 on page 46 : ep0r, endpoint transmission register and endpoint 2 reception register. moved power supply management chapter to section 12.4.3.1 on page 56 updated section 14 on page 76 added section 14.7 on page 84 changed figure 46 on page 90 removed references to true open drain pins changed section 16.1 on page 93 added warning in section 14.5.2 on page 82 added erratasheet on page 99 march-03 rev. 1.2 march 2003 99/102 errata sheet st7scr limitations and corrections 18 silicon identification this document refers only to st7fscr devices shown in table 25 . they are identifiable both by the last letter of the trace code marked on the device package and by the last 3 digits of the internal sales type printed on the box label (see also figure 51 ) table 25. device identification 19 reference specification st7scr datasheet 1.3 (march 2003). 20 silicon limitations 20.1 unexpected reset fetch if an interrupt request occurs while a "pop cc" instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector ad- dress to the cpu. to solve this issue, a "pop cc" instruction must always be preceded by a "sim" instruction. 20.2 usb: two consecutive setup tokens description when two consecutive setup tokens are received and the software does not have time to write the value 8 in the endpoint 0 reception counter register (cnt0rxr), the data associ- ated with the second setup are not copied to the buffer. impact the impact depends on the host behaviour. in the usb spec 2.0 it is stated (chapter 5.5.5 p43) that: a setup transaction should not normally be sent before the completion of a pre- vious control transfer. however, if a transfer is aborted, for example, due to errors on the bus, the host can send the next setup transaction prematurely from the endpoints perspective. if the new setup token is sent because an error occurs in the previous one, it should contain the same data so no application malfunction will occur. trace code marked on device internal sales type on box label flash devices: xxxxxxxxxx 7fscrxxxx$m1 7fscrxxxx$t1 errata sheet 100/102 this limitation will be corrected in the next silicon revision. in the new revision, when a setup token is received, the value loaded in the internal counter is fixed to 8 by hardware independ- ently of the value in the cnt0rxr register. 20.3 usb buffer shared memory access description when f cpu is at 4 mhz, a value written in the usb buffer may be corrupted when v dd is less than 4.4v. this limitation will be corrected in the next silicon revision. impact usb buffer access cannot be guaranteed over the full v dd range when f cpu is at 4 mhz. 20.4 wdg (watchdog) limitations in flash devices, the wdg prescaler value is not 65536 as described in section 12.1.3 on page 40 ( figure 25 ), it is actually 16. this will be corrected in the next revision of the silicon. 20.5 supply current in halt mode (suspend) limitations the current consumption (i dd ) in some devices may exceed the maximum specified in the documentation (up to 1ma). workaround declare 200ma max. power value in the usb configuration descriptor. 20.5.1 v pp pin limitation in the impacted flash devices, contrary to the datasheet specification (which specifies that it must be tied to v ss ), the v pp pin must be tied to v dd in operating mode. this will be fixed in the next silicon revision . 20.6 start-up the st7scr relies on internal lvd and it may not start-up correctly if the power supply is slow. workaround put a 1m w resistor between v dd and v ss to eliminate the offset on v dd that may cause this power-on problem. errata sheet 101/102 20.7 i/o port input high level (v ih ) the v ih min value is 0.8*v dd and not 0.7*v dd as specified for the final silicon. 21 device marking figure 51. revision marking on box label and device marking 22 errata sheet revision history revision main changes date 1.2 updated section 20.5 "supply current in halt mode (suspend) limi- tations" on page 100 added section 20.6 "start-up" on page 100 03/13/03 type xxxx internalxxx$xx trace code last 2 digits after $ in internal sales type indicate silicon rev. last letter of trace code on device indicates silicon rev. on box label errata sheet 102/102 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
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